1. Field of the Invention
The present invention relates generally to semiconductor device manufacturing technology, and particularly to a method for forming shallow trench isolation in a semiconductor device.
2. Description of the Related Art
Manufacturing processes of highly integrated semiconductor devices involve forming a variety of components, such as a transistor, capacitor, metal wiring, etc., in very restricted regions, and forming highly insulated regions to prevent parasitic current leakage between the components.
Conventionally, a local oxidation of silicon (LOCOS) field oxide, formed by oxidizing a silicon substrate, has been widely used for isolating the components of the semiconductor device. However, because of the increase in the integration density, a LOCOS field oxide has become disadvantageous to the formation of integrated circuits, because it generally includes a “bird's beak” that may invade an active device region. Accordingly, a lot of alternative isolation technologies, more advantageous to the higher integration of devices, have been developed. As a typical example of such alternative isolation technologies, shallow trench isolation (STI) having a superior insulating performance and a relatively small formation area has been widely used for isolating transistors in higher integrated metal oxide semiconductor (MOS) and bipolar devices.
In a typical STI process, a pad oxide and a pad nitride are formed on an entire silicon substrate in successive order to protect an active device area. A photoresist layer is formed and patterned on the pad nitride by a photolithography process. The photoresist pattern defines an opening over an isolation area of the substrate.
After the exposure of the pad nitride by the photoresist pattern, the pad nitride and pad oxide are partially removed by an anisotropic etching process using the photoresist pattern as an etching mask. This etching process is performed to expose the isolation area in which a trench structure may be formed. Subsequently, the exposed isolation area of the substrate is etched to a predetermined depth by an anisotropic etching process, so that a trench structure is formed in the substrate. The photoresist pattern is removed, and the substrate is then cleaned.
After the formation of the trench structure, a trench oxide, e.g., a chemical vapor deposited (CVD) dielectric such as silicon dioxide, is formed over the entire substrate, filling the trench. Since this trench oxide also covers the active device area, and it should be selectively removed for device processing to continue. This is accomplished by planarizing the substrate, typically via chemical-mechanical polishing (CMP), using the pad silicon nitride layer over the active device area as a stop layer. This process removes the trench oxide from the active device area while retaining it in the isolation trenches. The pad nitride and pad oxide are then removed, resulting in a highly planar substrate with isolated device areas.
FIG. 1 is a scanning electron microscopy (SEM) image of a semiconductor structure, right before the CMP process, including the substrate 10, the trench sidewall 20, the trench oxides 30a and 30b, the pad oxide 22, and the pad nitride 24. Here, reference numeral 40 indicates a silicon nitride layer formed on the trench oxide for the SEM observation.
FIG. 1 shows the STI structure having a wide trench dimension. In FIG. 1, the mark S indicates the point where the vertical line h1 extending from the bottom of the trench meets the top surface of the trench oxide 30a filling the trench. The mark M indicates the point where the vertical line h2 extending from the top surface of the pad nitride 24 meets the top surface of the trench oxide 30b deposited on the active device area. As shown in FIG. 1, there is a considerable difference in the altitude between the points S and M. This phenomenon, commonly observed in the case of a low density of trenches per unit area, means that the surface topology of the trench oxide is uneven between the active device area and the isolation area. The uneven surface topology of the trench oxide may result in a poor planarization in the CMP process. Specifically, since the CMP process continues until the pad nitride is exposed in the active device area, the trench oxide in the isolation area may be excessively polished. As a result, an upper portion of the trench oxide deposited in the isolation area may be deeply dug out, which is generally called a dishing condition, and the substrate may be damaged in the vicinity of the upper corners of the isolation trench.